The present invention relates to flip chips, and more particularly to an improvement in the adhesion of the underfill material to the silicon chip in a flip chip assembly to a substrate.
The conventional solution to this problem has been to underfill the chip with an adhesive which effectively bonds the chip to the substrate in order to reduce the load on the solder joints, The success of this method is limited, however, by the degree of adhesion of the underfill material to the chip passivation layer. As a result of thermal cycling, the underfill material tends to delaminate from the chip passivation layer, particularly at the chip edges and at the solder joints. This problem is exacerbated by flux residues and other contaminants, as well as by the nature of the passivation layer.
The conventional solution to this problem has been to underfill the chip with an adhesive which effectively bonds the chip to the substrate in order to reduce the load on the solder joints. The success of this method is limited, however, by the degree of adhesion of the underfill material to the chip passivation layer. As a result of thermal cycling, the underfill material tends to delaminate from the chip passivation, particularly at the chip edges and at the solder joints. This problem is exacerbated by flux residues and other contaminants, as well as by the nature of the passivation layer.
It is, therefore, an object of the present invention to provide improved mounting of a flip chip to a substrate, particularly when it will be subjected to thermal excursions.
It is another object of the present invention to provide improved adhesion of the underfill material to the silicon chip in a flip chip assembly.
The above and other objects are achieved in accordance with the present invention by a flip chip having a chip passivation layer disposed on a metalization layer. Terminal vias are formed in the passivation layer to expose a portion of the metalization layer with terminal metalization disposed on the metalization layer at the terminal vias. A stress reducing layer is disposed on the chip passivation layer with underfill apertures formed in the stress reducing layer so as to expose a portion of the chip passivation layer adjacent the terminal metalization. This allows the underfill to bond to the passivation layer proximate the solder joints, and substantially limits the shear stress along the passivation layer/underfill interface.
In another aspect of the present invention, the stress reducing layer terminates a distance from the edge of the chip, thereby exposing a portion of the chip passivation layer or silicon at the edge of the chip. This allows the underfill to bond to the passivation or metalization layer proximate the chip edge, and again substantially limits the shear stress along the chip edge underfill interface.